mirror of https://github.com/zachjs/sv2v.git
24 lines
401 B
Verilog
24 lines
401 B
Verilog
`default_nettype none
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module top;
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reg [4:0] __input;
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wire [3:0] result;
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Example dut(
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.a(__input[3:2]),
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.b(__input[1:0]),
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.result(result)
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);
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initial begin
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$monitor($time, "i: %b result: %b", __input, result);
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for (__input = 0; __input < 5'hf; __input = __input + 1) begin
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#10;
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end
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$finish;
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end
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endmodule |