mirror of https://github.com/zachjs/sv2v.git
28 lines
658 B
Verilog
28 lines
658 B
Verilog
`default_nettype none
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module Example(
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input wire [3:0] a,
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output wire [31:0] all
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);
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function [1:0] __truncate_to_2_bits(input [1:0] i);
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__truncate_to_2_bits = i;
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endfunction
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generate
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genvar i;
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for(i = 0; i < 4; i = i + 1) begin : __gen_loop
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reg [7:0] s;
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always @* begin
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s = {__truncate_to_2_bits(3-i), a, __truncate_to_2_bits(i)};
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// s = '{
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// first: i,
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// middle: a,
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// last: 3 - i
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// };
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end
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assign all[i*8+:8] = s;
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end
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endgenerate
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endmodule |