mirror of https://github.com/zachjs/sv2v.git
30 lines
574 B
Systemverilog
30 lines
574 B
Systemverilog
`default_nettype none
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typedef struct packed {
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logic [1:0] last;
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logic [3:0] middle;
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logic [1:0] first;
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} MyStruct_t;
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module Example(
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input logic [3:0] a,
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output logic [31:0] all
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);
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generate
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genvar i;
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for(i = 0; i < 4; i = i + 1) begin
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MyStruct_t s;
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always_comb begin
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s = '{
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first: i,
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middle: a,
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last: 3 - i
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};
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end
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assign all[i*$bits(s)+:$bits(s)] = s;
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end
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endgenerate
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endmodule |