mirror of https://github.com/zachjs/sv2v.git
64 lines
1.4 KiB
Systemverilog
64 lines
1.4 KiB
Systemverilog
`default_nettype none
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module Example(
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input logic [1:0] select,
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// This is an array of 3 (4-bit wide) elements
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output logic [2:0][3:0] data
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);
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UniqueCase case0(.select, .data(data[0]));
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WildcardCase case1(.select, .data(data[1]));
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DefaultCase case2(.select, .data(data[2]));
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endmodule
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module UniqueCase(
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input logic [1:0] select,
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output logic [3:0] data
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);
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always_comb begin
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data = 4'b0;
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unique case(select)
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2'd0: data = 4'ha;
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2'd1: data = 4'h6;
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2'd2: data = 4'h3;
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/* unique means that the toolchain can assume 2'd3 will never happen */
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endcase
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end
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endmodule
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module WildcardCase(
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input logic [1:0] select,
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output logic [3:0] data
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);
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always_comb begin
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data = 4'b0;
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unique casez(select)
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2'b00: data = 4'h3;
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2'b1?: data = 4'hd;
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// Unique means that the toolchain can assume 2'b01 will never happen
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endcase
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end
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endmodule
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module DefaultCase(
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input logic [1:0] select,
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output logic [3:0] data
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);
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always_comb begin
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data = 4'b0;
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case (select)
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2'b00: data = 4'h7;
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2'b01: data = 4'h9;
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default: data = 4'h8;
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endcase
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end
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endmodule
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// There is also a casex construct, but it is very dangerous and not recommend to be used in real designs.
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// https://www.verilogpro.com/verilog-case-casez-casex/
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