mirror of https://github.com/zachjs/sv2v.git
71 lines
1.5 KiB
Verilog
71 lines
1.5 KiB
Verilog
`default_nettype none
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module top;
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reg [1:0] index;
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reg [7:0] element;
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wire [31:0] arrayData;
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reg enable, clock, clear;
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Array #(.ELEMENTS(4), .WIDTH(8)) arrayInstance(
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.index(index),
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.element(element),
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.array(arrayData),
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.clock(clock),
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.clear(clear),
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.enable(enable)
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);
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wire [7:0] result;
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ArrayOrReduction #(.SIZE(4), .WIDTH(8)) reduction(
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.inputs(arrayData),
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.result(result)
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);
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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$monitor($time, " arrayData: %h result: %h", arrayData, result);
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clear = 1'b1;
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index = 2'b0;
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element = 8'h0;
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enable = 1'b0;
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repeat(3) @(posedge clock);
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clear = 1'b0;
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element = 8'haa;
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enable = 1'b1;
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@(posedge clock);
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element = 8'h11;
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index = 2'd1;
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@(posedge clock);
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element = 8'h72;
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index = 2'd2;
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@(posedge clock);
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element = 8'h88;
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index = 3'd3;
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@(posedge clock);
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element = 8'hff;
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index = 3'd0;
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enable = 1'b0;
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@(posedge clock);
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element = 8'h00;
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enable = 1'b1;
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@(posedge clock);
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element = 8'h00;
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index = 3'd1;
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@(posedge clock);
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enable = 1'b0;
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index = 3'd2;
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@(posedge clock);
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enable = 1'b1;
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index = 3'd3;
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@(posedge clock);
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enable = 1'b0;
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repeat(5) @(posedge clock);
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$finish;
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end
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endmodule
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