mirror of https://github.com/zachjs/sv2v.git
72 lines
2.5 KiB
Verilog
72 lines
2.5 KiB
Verilog
`default_nettype none
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module ArrayOrReduction #(
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parameter SIZE = 16, WIDTH=32) (
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// Flattened array
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input wire [(SIZE*WIDTH)-1:0] inputs,
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output wire [WIDTH-1:0] result
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);
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// One option is to modify the code to use the flattened array, but probably
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// an easier option is to just insert a generate block to unflatten
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// everything.
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wire [WIDTH-1:0] __inputs[SIZE-1:0];
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genvar index;
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generate
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for(index = 0; index < SIZE; index = index + 32'd1) begin : unflatten
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localparam START_BIT = index * WIDTH;
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assign __inputs[index] = inputs[START_BIT + WIDTH - 1:START_BIT];
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end
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endgenerate
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// Recursively generate a pair-wise reduction
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generate
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if(SIZE <= 0) begin : error_case
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DoesNotExit foo();
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end else if (SIZE == 1) begin : base_case_1
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assign result = __inputs[0];
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end else if(SIZE == 2) begin : base_case_2
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assign result = __inputs[0] | __inputs[1];
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end else begin : recursive_case
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wire [WIDTH-1:0] subResults [1:0];
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// The array needs to be re-flattened here or alternatively, just use computation on the original array
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ArrayOrReduction #(.WIDTH(WIDTH), .SIZE(SIZE/2)) top(.inputs(inputs[(SIZE*WIDTH)-1:(SIZE*WIDTH)/2]), .result(subResults[1]));
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ArrayOrReduction #(.WIDTH(WIDTH), .SIZE(SIZE/2)) bot(.inputs(inputs[(SIZE * WIDTH)/2-1:0]), .result(subResults[0]));
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assign result = subResults[0] | subResults[1];
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end
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endgenerate
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endmodule
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module Array #(parameter ELEMENTS=16, WIDTH=32)(
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input wire [$clog2(ELEMENTS)-1:0] index,
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input wire [WIDTH-1:0] element,
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// Flattened array
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output wire [(ELEMENTS*WIDTH)-1:0] array,
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input wire clock, clear, enable
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);
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reg [WIDTH-1:0] __array[ELEMENTS-1:0];
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genvar g_index;
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generate
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for(g_index = 0; g_index < ELEMENTS; g_index = g_index + 32'd1) begin : unflatten
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localparam START_BIT = g_index * WIDTH;
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assign array[START_BIT + WIDTH - 1:START_BIT] = __array[g_index];
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end
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endgenerate
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localparam ZERO_ELEMENT = {WIDTH{1'b0}};
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// I think this might synthesize correctly, but it is pretty gross.
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integer reset_index;
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always @(posedge clock)
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if(clear) begin
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for(reset_index = 0; reset_index < ELEMENTS; reset_index = reset_index + 32'd1)
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__array[reset_index] <= {ZERO_ELEMENT};
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end else if(enable)
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__array[index] <= element;
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endmodule
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