mirror of https://github.com/zachjs/sv2v.git
55 lines
1.4 KiB
Systemverilog
55 lines
1.4 KiB
Systemverilog
module top;
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reg clk;
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initial begin
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clk = 0;
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repeat (100) #1 clk = ~clk;
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$finish;
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end
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assert property (@(posedge clk) 1);
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assume property (@(posedge clk) 1);
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cover property (@(posedge clk) 1);
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initial begin
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assert (1);
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assume (1);
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cover (1);
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assert #0 (1);
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assume #0 (1);
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cover #0 (1);
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assert #0_0 (1);
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assume #0_0 (1);
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cover #0_0 (1);
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assert final (1);
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assume final (1);
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cover final (1);
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end
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assert final (1);
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assume final (1);
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cover final (1);
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a1: assert final (1);
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a2: assume final (1);
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a3: cover final (1);
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assert #0 (1);
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assume #0 (1);
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cover #0 (1);
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b1: assert #0 (1);
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b2: assume #0 (1);
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b3: cover #0 (1);
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assert property (@(posedge clk) 1)
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else $display("FOO");
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assume property (@(posedge clk) 1)
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$display("FOO");
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else
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$display("BAR");
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assert property (@(posedge clk)
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(1 |-> (1 |=> (1 #-# (1 #=# (1 iff 1))))));
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assert property (@(posedge clk)
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1 and 1 or 1 intersect 1 throughout 1 within 1);
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assert property (@(posedge clk) 1 ##1 1);
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assert property (@(posedge clk) ##1 1);
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integer x;
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assert property (@(posedge clk) first_match(1, x++, $display("a", clk), $display("b", clk)));
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endmodule
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