mirror of https://github.com/zachjs/sv2v.git
15 lines
310 B
Systemverilog
15 lines
310 B
Systemverilog
// pattern: instance m of Module has unconnected interface ports: i, k
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// location: interface_unbound_modports.sv:13:5
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interface Interface;
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logic x;
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endinterface
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module Module(i, j, k);
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Interface i;
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Interface j;
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Interface k;
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endmodule
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module top;
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Interface j();
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Module m(.j);
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endmodule
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