mirror of https://github.com/zachjs/sv2v.git
11 lines
327 B
Systemverilog
11 lines
327 B
Systemverilog
// pattern: port intf has type Interface1\.ModportB, but the binding intf1\.ModportA has type Interface1\.ModportA
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// location: interface_mismatch_3.sv:9:5
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`include "interface_mismatch.svh"
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module Module(intf);
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Interface1.ModportB intf;
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endmodule
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module top;
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Interface1 intf1();
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Module m(intf1.ModportA);
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endmodule
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