mirror of https://github.com/zachjs/sv2v.git
16 lines
446 B
Systemverilog
16 lines
446 B
Systemverilog
module top;
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localparam logic [7:0] init_val [4] = {8'd0, 8'd8, 8'd10, 8'd200};
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initial begin
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integer i, j;
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for (i = 0; i < 4; i += 1) begin
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$display(init_val[i]);
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for (j = 0; j < 8; j += 1) begin
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$display(init_val[i][j]);
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end
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end
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end
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typedef byte T [3];
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localparam T X = '{ 5, 3, 2 };
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initial $display("%0d %0d %0d", X[0], X[1], X[2]);
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endmodule
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