mirror of https://github.com/zachjs/sv2v.git
27 lines
768 B
Systemverilog
27 lines
768 B
Systemverilog
module top;
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function automatic [31:0] flatten;
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input byte inp [4];
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return {inp[0], inp[1], inp[2], inp[3]};
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endfunction
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task dump;
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input byte inp [4];
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$display("t(%b)", {inp[0], inp[1], inp[2], inp[3]});
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endtask
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byte arr1 [4];
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byte arr2 [4];
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wire integer unsigned flat = flatten(arr1) | 1'b1;
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initial begin
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#1 arr1[0] = 1;
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#1 arr1[1] = 3;
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#1 arr1[2] = 9;
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#1 arr1[3] = 7;
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#1 arr2[0] = 1; dump(arr2);
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#1 arr2[1] = 3; dump(arr2);
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#1 arr2[2] = 9; dump(arr2);
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#1 arr2[3] = 7; dump(arr2);
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end
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byte arr3 [4];
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wire [31:0] arr3_flat = {arr3[0], arr3[1], arr3[2], arr3[3]};
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initial $readmemh("tf_unpacked_input.mem", arr3);
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endmodule
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