mirror of https://github.com/zachjs/sv2v.git
27 lines
721 B
Verilog
27 lines
721 B
Verilog
module top;
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reg [2:0] test;
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reg [3:0] foo;
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reg [3:0] bar;
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integer x;
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reg [7:0] y;
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initial begin
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test = 0;
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$display(test);
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foo = 4'b0011;
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$display(foo);
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bar = 4'b1111;
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$display(bar);
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x = 1'b1; $display("%b %0d", x, x);
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y = 1'b1; $display("%b %0d", y, y);
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x = 2'b00; $display("%b %0d", x, x);
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y = 2'b00; $display("%b %0d", y, y);
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x = 2'b11; $display("%b %0d", x, x);
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y = 2'b11; $display("%b %0d", y, y);
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x = 2'bxx; $display("%b %0d", x, x);
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y = 2'bxx; $display("%b %0d", y, y);
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x = 2'bzz; $display("%b %0d", x, x);
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y = 2'bzz; $display("%b %0d", y, y);
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end
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endmodule
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