mirror of https://github.com/zachjs/sv2v.git
17 lines
411 B
Systemverilog
17 lines
411 B
Systemverilog
module top;
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assign arr[0][0] = 1;
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logic [1:0][2:0] arr;
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initial $display("%b", arr);
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parameter YES = 1;
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if (YES) begin : blk
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assign brr[0][0] = 1;
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logic [2:0][3:0] brr;
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initial $display("%b", brr);
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if (YES) begin : blk2
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assign crr[0][0] = 1;
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logic [3:0][4:0] crr;
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initial $display("%b", crr);
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end
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end
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endmodule
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