mirror of https://github.com/zachjs/sv2v.git
28 lines
483 B
Systemverilog
28 lines
483 B
Systemverilog
interface intf;
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byte x;
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endinterface
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module mod(intf j);
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intf i();
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assign j.x = 1;
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assign i.x = 2;
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genvar z;
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for (z = 0; z < 2; z++) begin : blk
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wire [7:0] x = $bits(j.x) - 5 + z;
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end
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endmodule
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module top;
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byte z = 0;
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intf i();
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mod m(i);
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`define DUMP(expr) $display(`"expr = %b`", expr);
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initial begin
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`DUMP(z)
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`DUMP(i.x)
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`DUMP(m.i.x)
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`DUMP(m.blk[0].x)
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`DUMP(m.blk[1].x)
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end
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endmodule
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