mirror of https://github.com/zachjs/sv2v.git
19 lines
356 B
Systemverilog
19 lines
356 B
Systemverilog
module ExampleA;
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typedef enum logic {
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A = 1,
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B = 0,
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C = 2
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} Enum;
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Enum x = A;
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initial $display("ExampleA: x=%b, A=%b, B=%b", x, A, B);
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endmodule
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module ExampleB;
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typedef enum logic {
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A = 0,
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B = 1
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} Enum;
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Enum x = A;
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initial $display("ExampleB: x=%b, A=%b, B=%b", x, A, B);
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endmodule
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