mirror of https://github.com/zachjs/sv2v.git
20 lines
406 B
Verilog
20 lines
406 B
Verilog
`define DUMP(expr, value) initial $display(`"expr = %0d`", value);
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module top;
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`DUMP(W, 4)
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`DUMP(C#(3)::X, 3)
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`DUMP(C#(3)::Y, 6)
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`DUMP(P::Z, 3)
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`DUMP(f(3), 24)
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if (1) initial begin
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$display("intf");
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$display("Bye!");
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$display("Way!");
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end
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initial begin
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$display("t()");
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$display("Hello!");
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$display("No!");
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end
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endmodule
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