mirror of https://github.com/zachjs/sv2v.git
40 lines
896 B
Systemverilog
40 lines
896 B
Systemverilog
`ifdef REF
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`define CHECK(N) (P & (1 << (Z+N+1) - 1))
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`else
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`define CHECK(N) ((Z+N+1)'(P) & (1 << (Z+N+1) - 1))
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`endif
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`define PRINT(N) initial #P $display(`"%b bit N is set`", P);
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module mod;
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parameter unsigned P = 1;
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parameter Z = 0;
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if (!Z) begin : blk1
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if (`CHECK(0)) `PRINT(0)
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else if (`CHECK(1)) `PRINT(1)
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else if (`CHECK(2)) `PRINT(2)
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end
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if (!Z) begin : blk2
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genvar i;
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if (`CHECK(3))
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`PRINT(3)
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else
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for (i = 1; i == 1 && `CHECK(4); i = i + 1)
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`PRINT(4)
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end
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if (!Z) begin : blk3
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wire signed x = 1;
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`ifdef REF
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wire [P - 1:0] tmp = x;
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wire [7:0] y = tmp;
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`else
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wire [7:0] y = $unsigned(P'(x));
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`endif
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end
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wire [7:0] x = blk3.y;
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initial #P $display("%b x = %b", P, x);
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endmodule
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