mirror of https://github.com/zachjs/sv2v.git
67 lines
1.9 KiB
Systemverilog
67 lines
1.9 KiB
Systemverilog
module top;
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parameter WIDTH = 32;
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generate
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begin : A
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int x = -235;
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end
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endgenerate
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initial begin
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logic [31:0] w = 1234;
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int y = 1234;
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logic [4:0] z = y;
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$display("%0d %0d", w, 5'(w));
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$display("%0d %0d", A.x, 5'(A.x));
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$display("%0d %0d", y, 5'(y));
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$display("%0d %0d", z, 5'(z));
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$display("%0d %0d", w+1, 5'(w+1));
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$display("%0d %0d", A.x+1, 5'(A.x+1));
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$display("%0d %0d", y+1, 5'(y+1));
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$display("%0d %0d", z+1, 5'(z+1));
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$display("%b %b", w, 40'(w));
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$display("%b %b", A.x, 40'(A.x));
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$display("%b %b", y, 40'(y));
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$display("%b %b", z, 40'(z));
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$display("%0d %0d", w, ($clog2(WIDTH))'(w));
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$display("%0d %0d", A.x, ($clog2(WIDTH))'(A.x));
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$display("%0d %0d", y, ($clog2(WIDTH))'(y));
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$display("%0d %0d", z, ($clog2(WIDTH))'(z));
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$display("%b", 32'(4));
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$display("%b", 33'(4));
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$display("%b", 33'(64'hFFFF_FFFF_FFFF_FFFF));
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end
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localparam bit foo = '0;
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localparam logic [31:0] bar = 32'(foo);
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initial $display("%b %b", foo, bar);
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initial begin
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$display("%b", 5'('1));
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$display("%b", 5'(1'sb1));
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end
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parameter W = 9;
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initial begin
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byte i = -1;
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byte unsigned j = -1;
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$display("%b", W'(i));
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$display("%b", W'(j));
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end
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typedef integer T1;
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typedef integer signed T2;
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typedef integer unsigned T3;
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initial begin
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$display("T1 %0d", T1'(1'sb1));
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$display("T2 %0d", T2'(1'sb1));
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$display("T3 %0d", T3'(1'sb1));
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$display("T1 %0d", T1'(32'sd1));
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$display("T2 %0d", T2'(32'sd1));
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$display("T3 %0d", T3'(32'sd1));
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$display("T1 %0d", T1'(32'd1));
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$display("T2 %0d", T2'(32'd1));
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$display("T3 %0d", T3'(32'd1));
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end
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endmodule
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