sv2v/test/basic/sense_star.sv

18 lines
312 B
Systemverilog

module top;
`define TEST(sense) always sense $display(`"sense %b`", x);
reg x, y;
`TEST(@*)
`TEST(@ *)
`TEST(@x)
`TEST(@y)
`TEST(@ ( * ))
`TEST(@ ( *))
`TEST(@ (* ))
`TEST(@ (*))
`TEST(@( * ))
`TEST(@( *))
`TEST(@(* ))
`TEST(@(*))
initial x = 1;
endmodule