mirror of https://github.com/zachjs/sv2v.git
15 lines
410 B
Systemverilog
15 lines
410 B
Systemverilog
module mod(
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input \AFancySignalName[3].Something ,
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output \AFancySignalName[3].SomethingElse
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);
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endmodule
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module top;
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wire \BFancySignalName.Something = 1;
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wire \BFancySignalName.SomethingElse ;
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mod inst_of_fancy_module(
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.\AFancySignalName[3].Something (\BFancySignalName.Something ),
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.\AFancySignalName[3].SomethingElse (\BFancySignalName.SomethingElse )
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);
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endmodule
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