mirror of https://github.com/zachjs/sv2v.git
81 lines
1.6 KiB
Systemverilog
81 lines
1.6 KiB
Systemverilog
`default_nettype none
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interface SimpleInterface(input logic clock, clear);
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logic [31:0] data;
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logic shift;
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modport Producer(
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output data,
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input shift,
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input clock, clear
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);
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modport Consumer(
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input data,
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output shift,
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input clock, clear
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);
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endinterface : SimpleInterface
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module Device(
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input logic [7:0] dataIn,
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output logic [31:0] dataOut,
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input logic clock, clear
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);
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SimpleInterface theInterface(.clock, .clear);
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Producer producer(
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.myInterface(theInterface.Producer),
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.dataIn
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);
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Consumer consumer(
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.myInterface(theInterface.Consumer),
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.dataOut
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);
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endmodule
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// The producer takes the input and then transforms it for 4 cycles
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module Producer(
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SimpleInterface.Producer myInterface,
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input logic [7:0] dataIn
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);
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logic [31:0] inProgress;
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always_ff @(posedge myInterface.clock) begin
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if(myInterface.clear) begin
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inProgress <= 32'b0;
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end else if(myInterface.shift) begin
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inProgress <= {inProgress[23:0], dataIn};
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end
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end
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assign myInterface.data = inProgress;
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endmodule
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module Consumer(
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SimpleInterface.Consumer myInterface,
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output logic [31:0] dataOut
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);
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// Just want this variable to make the test bench nicer
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logic local_shift;
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assign local_shift = myInterface.shift;
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always_ff @(posedge myInterface.clock)
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if(myInterface.clear) begin
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myInterface.shift <= 1'b0;
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end else begin
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myInterface.shift <= ~myInterface.shift;
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end
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assign dataOut = myInterface.data;
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endmodule |