SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

Zachary Snow bfafea5dd8 Fix compiliation; trailing whitespace; added .gitignore		2019-02-07 23:58:34 -05:00
Data	Fix compiliation; trailing whitespace; added .gitignore	2019-02-07 23:58:34 -05:00
Language	Fix compiliation; trailing whitespace; added .gitignore	2019-02-07 23:58:34 -05:00
.gitignore	Fix compiliation; trailing whitespace; added .gitignore	2019-02-07 23:58:34 -05:00
LICENSE	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
Setup.hs	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
verilog.cabal	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00