mirror of https://github.com/zachjs/sv2v.git
17 lines
924 B
Verilog
17 lines
924 B
Verilog
module top;
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initial begin
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$display("Info [%0t] severity_task.sv:3:9 - top.<unnamed_block>", $time);
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$display("Info [%0t] severity_task.sv:4:9 - top.<unnamed_block>\n msg: ", $time, "%b", 1);
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$display("Warning [%0t] severity_task.sv:5:9 - top.<unnamed_block>", $time);
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$display("Warning [%0t] severity_task.sv:6:9 - top.<unnamed_block>\n msg: ", $time, "%b", 2);
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$display("Error [%0t] severity_task.sv:7:9 - top.<unnamed_block>", $time);
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$display("Error [%0t] severity_task.sv:8:9 - top.<unnamed_block>\n msg: ", $time, "%b", 3);
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$display("Fatal [%0t] severity_task.sv:9:9 - top.<unnamed_block>", $time);
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$finish;
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$display("Fatal [%0t] severity_task.sv:10:9 - top.<unnamed_block>", $time);
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$finish(0);
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$display("Fatal [%0t] severity_task.sv:11:9 - top.<unnamed_block>\n msg: ", $time, "%b", 4);
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$finish(1);
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end
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endmodule
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