mirror of https://github.com/zachjs/sv2v.git
21 lines
812 B
Verilog
21 lines
812 B
Verilog
module top;
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initial $display("Info [elaboration] elab_task.sv:2:5 - top");
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initial $display("Info [elaboration] elab_task.sv:3:5 - top\n msg: %b", 1);
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initial $display("Warning [elaboration] elab_task.sv:4:5 - top");
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initial $display("Warning [elaboration] elab_task.sv:5:5 - top\n msg: %b", 2);
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initial $display("Error [elaboration] elab_task.sv:6:5 - top");
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initial $display("Error [elaboration] elab_task.sv:7:5 - top\n msg: %b", 3);
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initial begin
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$display("Fatal [elaboration] elab_task.sv:8:5 - top");
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$finish;
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end
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initial begin
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$display("Fatal [elaboration] elab_task.sv:9:5 - top");
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$finish(0);
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end
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initial begin
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$display("Fatal [elaboration] elab_task.sv:10:5 - top\n msg: %b", 4);
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$finish(1);
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end
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endmodule
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