mirror of https://github.com/zachjs/sv2v.git
24 lines
744 B
Systemverilog
24 lines
744 B
Systemverilog
module top;
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initial begin
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logic [31:0] w = 1234;
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int x = -235;
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int y = 1234;
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logic [4:0] z = y;
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$display("%0d %0d", w, 5'(w));
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$display("%0d %0d", x, 5'(x));
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$display("%0d %0d", y, 5'(y));
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$display("%0d %0d", z, 5'(z));
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$display("%0d %0d", w+1, 5'(w+1));
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$display("%0d %0d", x+1, 5'(x+1));
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$display("%0d %0d", y+1, 5'(y+1));
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$display("%0d %0d", z+1, 5'(z+1));
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$display("%b %b", w, 40'(w));
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$display("%b %b", x, 40'(x));
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$display("%b %b", y, 40'(y));
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$display("%b %b", z, 40'(z));
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end
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localparam bit foo = '0;
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localparam logic [31:0] bar = 32'(foo);
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initial $display("%b %b", foo, bar);
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endmodule
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