mirror of https://github.com/zachjs/sv2v.git
44 lines
1.3 KiB
Verilog
44 lines
1.3 KiB
Verilog
module Streamer(i, l1, r1, l2, r2);
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parameter IN_WIDTH = 0;
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parameter OUT_WIDTH = 0;
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parameter CHUNK_SIZE = 0;
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input wire [IN_WIDTH-1:0] i;
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output wire [OUT_WIDTH-1:0] l1;
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output wire [OUT_WIDTH-1:0] r1;
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output reg [OUT_WIDTH-1:0] l2;
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output reg [OUT_WIDTH-1:0] r2;
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function [IN_WIDTH-1:0] stream_left;
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input [IN_WIDTH-1:0] inp;
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integer idx;
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localparam remainder = IN_WIDTH % CHUNK_SIZE;
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localparam remainder_fake = remainder ? remainder : 1;
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begin
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for (idx = 0; idx + CHUNK_SIZE <= IN_WIDTH; idx = idx + CHUNK_SIZE)
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stream_left[IN_WIDTH - idx - 1 -: CHUNK_SIZE] = inp[idx+:CHUNK_SIZE];
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if (remainder)
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stream_left[0+:remainder_fake] = inp[idx+:remainder_fake];
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end
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endfunction
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function [OUT_WIDTH-1:0] pad;
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input [IN_WIDTH-1:0] inp;
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pad = IN_WIDTH > OUT_WIDTH
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? inp >> IN_WIDTH - OUT_WIDTH
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: inp << OUT_WIDTH - IN_WIDTH
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;
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endfunction
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generate
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if (IN_WIDTH <= OUT_WIDTH) begin
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assign l1 = pad(stream_left(i));
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assign r1 = pad(i);
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end
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if (OUT_WIDTH <= IN_WIDTH) begin
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always @* l2 = pad(stream_left(i));
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always @* r2 = pad(i);
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end
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endgenerate
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endmodule
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