mirror of https://github.com/zachjs/sv2v.git
14 lines
351 B
Systemverilog
14 lines
351 B
Systemverilog
module top;
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parameter A = 3;
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parameter B = 4;
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logic [A*B-1:0] arr;
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initial begin
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arr = 0;
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for (integer i = 0; i < A; ++i) begin
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// yes this is silly but it captures an interesting edge case
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arr[i * B +: B] = $bits(arr[i * B +: B])'(i);
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end
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$display("%b", arr);
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end
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endmodule
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