mirror of https://github.com/zachjs/sv2v.git
44 lines
689 B
Verilog
44 lines
689 B
Verilog
module Flip(x, y);
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input x;
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output y;
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assign y = ~x;
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endmodule
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module Test1(o);
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output [1:0] o;
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wire x = 0;
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generate
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genvar i;
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for (i = 0; i < 1; i = i + 1) begin
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Flip flip(x, o[i]);
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end
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endgenerate
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initial begin : blah
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integer i;
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i = 0;
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end
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endmodule
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module Test2(o);
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output o;
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wire x = 0;
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Flip flip(x, o);
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initial begin : blah
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integer o;
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o = 0;
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end
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endmodule
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module Test3(o);
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output o;
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reg x_0;
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wire x_1;
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Flip flip(x_0, x_1);
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assign o = x_0;
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initial x_0 = 0;
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initial begin : blah
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integer x;
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x = 0;
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end
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endmodule
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