mirror of https://github.com/zachjs/sv2v.git
38 lines
590 B
Systemverilog
38 lines
590 B
Systemverilog
module Flip(x, y);
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input x;
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output y;
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assign y = ~x;
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endmodule
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module Test1(o);
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output [1:0] o;
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logic x = 0;
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for (genvar i = 0; i < 1; ++i) begin
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Flip flip(x, o[i]);
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end
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initial begin
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integer i = 0;
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end
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endmodule
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module Test2(o);
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output o;
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logic x = 0;
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Flip flip(x, o);
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initial begin
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integer o = 0;
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x = 0;
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end
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endmodule
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module Test3(o);
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output o;
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logic [1:0] x;
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Flip flip(x[0], x[1]);
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assign o = x[0];
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initial x[0] = 0;
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initial begin
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integer x = 0;
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end
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endmodule
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