mirror of https://github.com/zachjs/sv2v.git
26 lines
813 B
Systemverilog
26 lines
813 B
Systemverilog
module top;
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generate
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for (genvar i = 1; i < 5; ++i) begin
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initial begin
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integer x, y;
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x = $unsigned(i'(1'sb1));
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y = $unsigned((i + 5)'(1'sb1));
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$display("%0d %b %b", i, x, y);
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end
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for (genvar j = 3; j < 6; ++j) begin
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initial begin
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integer x;
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x = $unsigned((i * j)'(1'sb1));
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$display("%0d %0d %b", i, j, x);
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end
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end
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end
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// TODO: This is not yet supported by iverilog
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// localparam P = 2;
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// for (genvar i = 0; i < int'(P); i = i + 1) begin : g
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// wire a = i;
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// end
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// initial $display("%b %b", g[0].a, g[1].a);
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endgenerate
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endmodule
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