mirror of https://github.com/zachjs/sv2v.git
65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
module top;
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generate
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begin : A
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reg signed [31:0] x;
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end
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endgenerate
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initial begin : foo_block
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reg [31:0] w;
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reg signed [31:0] y;
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reg [4:0] z;
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w = 1234;
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A.x = -235;
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y = 1234;
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z = y;
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$display("%0d %0d", w, w[4:0]);
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$display("%0d %0d", A.x, $signed(A.x[4:0]));
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$display("%0d %0d", y, $signed(y[4:0]));
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$display("%0d %0d", z, z[4:0]);
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$display("%0d %0d", w+1, w[4:0]+1);
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$display("%0d %0d", A.x+1, $signed(A.x[4:0])+1);
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$display("%0d %0d", y+1, $signed(y[4:0])+1);
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$display("%0d %0d", z+1, z[4:0]+1);
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$display("%b %b", w, {8'b0, w});
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$display("%b %b", A.x, {8'hFF, A.x});
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$display("%b %b", y, {8'b0, y});
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$display("%b %b", z, {35'b0, z});
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$display("%0d %0d", w, w[4:0]);
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$display("%0d %0d", A.x, $signed(A.x[4:0]));
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$display("%0d %0d", y, $signed(y[4:0]));
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$display("%0d %0d", z, z[4:0]);
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$display("%b", 32'd4);
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$display("%b", 33'd4);
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$display("%b", 33'h1_FFFF_FFFF);
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$display("%b", 32'd0);
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$display("%b", 33'd4294967296);
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$display("%b", 32'd1);
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$display("%b", 33'd4294967297);
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end
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localparam [0:0] foo = 0;
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localparam [31:0] bar = 32'b0;
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initial $display("%b %b", foo, bar);
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initial begin
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$display("%b", 5'sb11111);
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$display("%b", 5'sb11111);
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end
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parameter W = 9;
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initial begin : block
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reg signed [7:0] i;
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reg [7:0] j;
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reg [8:0] i_extended;
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reg [8:0] j_extended;
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i = -1;
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j = -1;
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i_extended = i;
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j_extended = j;
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$display("%b", i_extended);
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$display("%b", j_extended);
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end
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endmodule
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