mirror of https://github.com/zachjs/sv2v.git
24 lines
387 B
Systemverilog
24 lines
387 B
Systemverilog
module Example(
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input a, b,
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(* who=1 *) output c,
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(* what=2 *) output d, e,
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input f,
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(* when=3 *) (* where=4 *) output g, h, i
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);
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endmodule
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(* a=1 *) module top;
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(* foo="bar" *) reg x;
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initial begin
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x = 1;
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$display(x);
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end
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reg a, b;
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wire c;
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wire d, e;
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reg f;
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wire g, h, i;
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Example m(a,b,c,d,e,f,g,h,i);
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endmodule
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