SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

Zachary Snow b01003fab1 cleaner PAF output; PAF puts new items right after the old ones		2019-02-22 17:21:16 -05:00
Convert	cleaner PAF output; PAF puts new items right after the old ones	2019-02-22 17:21:16 -05:00
Language	fix some silly edge cases in round-tripping output	2019-02-22 13:55:48 -05:00
.gitignore	switch to using stack	2019-02-11 23:48:49 -05:00
Convert.hs	added (very hacky) PackedArrayFlatten conversion; convert logics in generate	2019-02-21 20:12:34 -05:00
LICENSE	updated LICENSE to reflect fork	2019-02-08 16:51:20 -05:00
Makefile	switch to using stack	2019-02-11 23:48:49 -05:00
Setup.hs	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
stack.yaml	switch to using stack	2019-02-11 23:48:49 -05:00
sv2v.cabal	added (very hacky) PackedArrayFlatten conversion; convert logics in generate	2019-02-21 20:12:34 -05:00
sv2v.hs	added logic to module items; toying with initial Conversion	2019-02-17 23:39:01 -05:00