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Zachary Snow
306d71334b
- use iverilog's -gstrict-expr-width throughout test suite - add warnings for excess bits or padding zeroes in number literals - add new --oversized-numbers parameter to retain support for unsized numbers wider than 32 bits - localized use of oversized numbers to new truncate test suite which verifies the behavior of both modes, and compares against the known behavior of iverilog
35 lines
665 B
Verilog
35 lines
665 B
Verilog
module top;
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reg [56-1:0] in;
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reg [2:0] select;
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wire a;
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wire [3:0] b;
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wire [1:0] c;
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Unpacker unpacker(in, select, a, b, c);
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initial begin
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$monitor("%d: %01b %04b %02b", select, a, b, c);
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in = 56'b01111011011011101111100111110111001010001011100110101000;
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select = 0; #1;
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select = 1; #1;
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select = 2; #1;
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select = 3; #1;
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select = 4; #1;
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select = 5; #1;
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select = 6; #1;
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select = 7; #1;
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$finish;
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end
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// 0 1010 00
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// 1 1100 11
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// 0 1000 10
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// 0 1110 01
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// 0 0111 11
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// 1 0111 11
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// 1 0110 11
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// 0 1111 01
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endmodule
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