mirror of https://github.com/zachjs/sv2v.git
33 lines
964 B
Systemverilog
33 lines
964 B
Systemverilog
module top;
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typedef struct packed {
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integer x;
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byte y;
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} S;
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typedef struct packed {
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byte x;
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shortint y;
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S z;
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} T;
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var T a;
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initial a = T'{ x: 5, y: 6, z: '{ x: 7, y: 8 } };
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var T b;
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T c;
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assign c = T'{ x: 9, y: 10, z: '{ x: 11, y: 12 } };
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initial begin
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b = T'{ x: 13, y: 14, z: '{ x: 15, y: 16 } };
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#1;
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$display("a %b", a);
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$display("b %b", b);
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$display("c %b", c);
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$display("x %b", T'{ x: 1, y: 2, z: '{ x: 3, y: 4 } });
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$display("$bits(S) = %0d", $bits(S));
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$display("$bits(T) = %0d", $bits(T));
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$display("$bits(a) = %0d", $bits(a));
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$display("$bits(a.x) = %0d", $bits(a.x));
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$display("$bits(a.y) = %0d", $bits(a.y));
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$display("$bits(a.z) = %0d", $bits(a.z));
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$display("$bits(a.z.x) = %0d", $bits(a.z.x));
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$display("$bits(a.z.y) = %0d", $bits(a.z.y));
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end
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endmodule
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