mirror of https://github.com/zachjs/sv2v.git
17 lines
430 B
Systemverilog
17 lines
430 B
Systemverilog
module top;
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localparam type T = logic;
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initial begin
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$display("A %0d", $bits(T));
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begin
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localparam type T = logic [1:0];
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$display("B %0d", $bits(T));
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begin
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localparam type T = T [1:0];
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$display("C %0d", $bits(T));
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end
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$display("B %0d", $bits(T));
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end
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$display("A %0d", $bits(T));
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end
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endmodule
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