mirror of https://github.com/zachjs/sv2v.git
55 lines
1.3 KiB
Systemverilog
55 lines
1.3 KiB
Systemverilog
interface Interface #(parameter WIDTH = 4) (
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input clock,
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output [$clog2(WIDTH) - 1:0] indices [2]
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);
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logic [2*WIDTH-1:0] x;
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modport ModportA(
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input clock,
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output indices,
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input .x(x[2*WIDTH-1:WIDTH]), .y(x[WIDTH-1:0])
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);
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modport ModportB(
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input clock,
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output .x(x)
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);
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endinterface
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module ModuleA(Interface.ModportA m);
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assign m.indices[0] = $clog2(m.x);
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assign m.indices[1] = $clog2(m.y);
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endmodule
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module ModuleB(Interface.ModportB m);
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parameter WIDTH = 0;
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initial m.x = 1;
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always @(posedge m.clock) begin
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logic temp;
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temp = m.x[WIDTH-1];
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for (integer i = WIDTH-1; i > 0; --i) begin
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m.x[i] = m.x[i-1];
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end
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m.x[0] = temp;
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end
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endmodule
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module ModuleBWrapper(Interface.ModportB m);
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parameter WIDTH = 0;
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ModuleB #(WIDTH) b(m);
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integer i = 0;
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initial #1 $display("shadow i = %d, %b", i, m.x);
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endmodule
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module ModuleAWrapper(Interface.ModportA m);
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ModuleA a(m);
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endmodule
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module Tester(input clock);
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parameter WIDTH = 1;
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logic [WIDTH-1:0] idx1, idx2;
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Interface #(2 ** WIDTH) i(clock, '{idx1, idx2});
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ModuleAWrapper a(i);
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ModuleBWrapper #(2 * 2 ** WIDTH) b(i);
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always @(negedge clock)
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$display("%d %0d %2d %2d %b", $time, WIDTH, idx1, idx2, i.x);
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endmodule
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