mirror of https://github.com/zachjs/sv2v.git
73 lines
1.7 KiB
Systemverilog
73 lines
1.7 KiB
Systemverilog
interface InterfaceA;
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task hello;
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input integer inp;
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$display("Hello from InterfaceA %0d", inp);
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endtask
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logic [20:0] x = 21'b01011_00100000_01011110;
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endinterface
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interface InterfaceB;
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task hello;
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input integer inp;
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$display("Hello from InterfaceB %0d", inp);
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endtask
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logic [10:0] x = 11'b011_11110100;
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endinterface
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// could get bound to any of the interfaces or modports
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module Module(interface i);
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initial #4 i.hello(1);
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initial #5 $display("Module got %b", i.x);
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endmodule
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interface InterfaceM;
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logic [4:0] x = 0;
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task hello;
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input integer inp;
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x = x + 1;
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$display("Hello from InterfaceM %0d %b", inp, x);
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endtask
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modport A(input .x(x[0]));
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modport B(input .x(x[2:1]));
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endinterface
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// could get bound to the entire interface bundle, or either modport
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module ModuleM(InterfaceM i);
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initial i.hello(-1);
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initial $display("ModuleM got %b", i.x);
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endmodule
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module ModuleWrapperMA(InterfaceM.A i); Module m(i); endmodule
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module ModuleWrapperMB(InterfaceM.B i); Module m(i); endmodule
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module ModuleWrapperM (InterfaceM i); Module m(i); endmodule
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module ModuleMWrapperMA(InterfaceM.A i); ModuleM m(i); endmodule
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module ModuleMWrapperMB(InterfaceM.B i); ModuleM m(i); endmodule
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module ModuleMWrapperM (InterfaceM i); ModuleM m(i); endmodule
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module top;
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InterfaceM im();
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Module c(im.A);
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Module d(im.B);
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Module e(im);
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ModuleM x(im.A);
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ModuleM y(im.B);
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ModuleM z(im);
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InterfaceA ia();
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InterfaceB ib();
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Module a(ia);
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Module b(ib);
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ModuleWrapperMA cw(im);
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ModuleWrapperMB dw(im);
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ModuleWrapperM ew(im);
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ModuleMWrapperMA xw(im);
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ModuleMWrapperMB yw(im);
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ModuleMWrapperM zw(im);
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endmodule
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