mirror of https://github.com/zachjs/sv2v.git
40 lines
844 B
Systemverilog
40 lines
844 B
Systemverilog
module top;
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reg input_a;
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reg input_b;
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wire output_and;
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wire output_and_delay;
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wire output_not;
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wire output_buf_delay;
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and (output_and, input_a, input_b);
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and #1 (output_and_delay, input_a, input_b);
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not (output_not, input_a);
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buf #2 foo_name (output_buf_delay, input_a);
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initial repeat(2) begin
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$monitor("%3d ", $time,
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input_a, input_b,
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output_and, output_and_delay,
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output_not, output_buf_delay);
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#1;
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#1; input_a = 1;
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#1; input_b = 0;
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#1; input_b = 1;
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#1;
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#1; input_a = 0;
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#1; input_b = 0;
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#1; input_a = 0;
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#1; input_b = 1;
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#1; input_a = 1;
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#1; input_b = 0;
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#1; input_a = 1;
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#1; input_b = 1;
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#1;
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#1;
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#1;
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end
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endmodule
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