mirror of https://github.com/zachjs/sv2v.git
19 lines
436 B
Systemverilog
19 lines
436 B
Systemverilog
module top;
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logic [1:0] foo [4] = {2'b10,2'b01,2'b11,2'b00};
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initial
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foreach (foo [ x ])
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$display(x, foo[x]);
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// from the SystemVerilog-2017 specification
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int A [2][3][4];
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bit [3:0][2:1] B [5:1][4];
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initial begin
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A = 0;
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B = 0;
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foreach( A [ i, j, k ] )
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$display(i, j, k);
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foreach( B [ q, r, , s ] )
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$display(q, r, s);
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end
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endmodule
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