mirror of https://github.com/zachjs/sv2v.git
22 lines
378 B
Verilog
22 lines
378 B
Verilog
module top;
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reg [5:0] a;
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wire [5:0] b;
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always @(*) a = b;
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reg x;
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wire [5:0] c;
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wire [5:0] d;
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wire [5:0] e;
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initial x = 0;
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assign c = x ? d : e;
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generate
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begin : A
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wire [1:0] c [0:2];
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wire [5:0] d;
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end
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endgenerate
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assign A.d = 0;
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initial $display("%b %b", A.c[0], A.d[1:0]);
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endmodule
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