mirror of https://github.com/zachjs/sv2v.git
39 lines
1020 B
Verilog
39 lines
1020 B
Verilog
`default_nettype none
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// So Verilog is very sad when it comes to enumerations. The easiest way to emulate this behavior is probably to define a macro for the enumeration and then instantiate it everywhere the type is used.
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`define MODE_T\
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parameter MODE_A = 32'b0;\
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parameter MODE_B = 32'b1
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`define OPERATION_T\
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parameter READ = 2'd1;\
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parameter WRITE = 2'd2;\
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parameter NONE = 2'd0
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module Example(
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input wire rawMode,
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output wire [1:0] rawOperation
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);
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`MODE_T;
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`OPERATION_T;
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// Enumeration variables don't have types, so they need to be default wires.
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// Technically this could be just one bit if the tool is smart enough to realize.
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wire [31:0] mode;
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reg [1:0] operation;
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// No need for a cast since everything is a wire
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assign mode = rawMode;
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assign rawOperation = operation;
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always @* begin
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case(mode)
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MODE_A: operation = READ;
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MODE_B: operation = WRITE;
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default: operation = NONE;
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endcase
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end
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endmodule |