mirror of https://github.com/zachjs/sv2v.git
82 lines
1.8 KiB
Bash
Executable File
82 lines
1.8 KiB
Bash
Executable File
#!/bin/sh
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SV2V=../../bin/sv2v
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assertExists() {
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file=$1
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[ -f "$file" ]
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assertTrue "$file does not exist" $?
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}
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# USAGE: simulate <vcd-outfile> <top-module> <file> [<file> ...]
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simulate() {
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# arguments
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sim_outfile="$1"; shift
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sim_top="$1"; shift
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# compile the files
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sim_prog="$SHUNIT_TMPDIR/simprog.exe"
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iverilog \
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-o "$sim_prog" \
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-g2005 \
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-DTEST_VCD="\"$sim_outfile\"" \
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-DTEST_TOP=$sim_top \
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"tb_dumper.v" \
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"$@"
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assertTrue "iverilog on $1 failed" $?
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# run the simulation
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$sim_prog > /dev/null
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assertTrue "simulating $1 failed" $?
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# remove the date from the VCD
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sed -i.orig -e "1,3d" "$sim_outfile"
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}
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assertConverts() {
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ac_file="$1"
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ac_temp="$SHUNIT_TMPDIR/ac-conv-temp.v"
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$SV2V "$ac_file" 2> /dev/null > "$ac_temp"
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assertTrue "1st conversion of $ac_file failed" $?
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$SV2V "$ac_temp" 2> /dev/null > /dev/null
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assertTrue "2nd conversion of $ac_file failed" $?
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}
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runTest() {
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test=$1
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assertNotNull "test not specified" $test
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sv="$test.sv"
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ve="$test.v"
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tb="${test}_tb.v"
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assertExists $sv
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assertExists $ve
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assertExists $tb
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assertConverts "$sv"
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assertConverts "$ve"
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assertConverts "$tb"
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# convert the SystemVerilog source file
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cv="$SHUNIT_TMPDIR/conv-$test.v"
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$SV2V $sv 2> /dev/null > $cv
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assertTrue "conversion failed" $?
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assertExists $cv
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ref_vcd="$SHUNIT_TMPDIR/ref.vcd"
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gen_vcd="$SHUNIT_TMPDIR/gen.vcd"
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# simulate and compare the two files
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simulate "$ref_vcd" top "$ve" "$tb"
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simulate "$gen_vcd" top "$cv" "$tb"
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diff "$ref_vcd" "$gen_vcd" > /dev/null
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assertTrue "VCDs are different" $?
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}
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suite() {
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for test in `ls *.sv | sed -e "s_\.sv\\\$__"`; do
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eval "test_$test() { runTest \"$test\"; }"
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suite_addTest "test_$test"
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done
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}
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. shunit2
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