mirror of https://github.com/zachjs/sv2v.git
58 lines
1.4 KiB
Haskell
58 lines
1.4 KiB
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- SystemVerilog to Verilog conversion
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-}
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module Convert (convert) where
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import Language.SystemVerilog.AST
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import Job (Target(..))
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import qualified Convert.AlwaysKW
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import qualified Convert.AsgnOp
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import qualified Convert.CaseKW
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import qualified Convert.Enum
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import qualified Convert.Logic
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import qualified Convert.PackedArray
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import qualified Convert.Return
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import qualified Convert.SplitPortDecl
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import qualified Convert.StarPort
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import qualified Convert.Struct
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import qualified Convert.Typedef
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import qualified Convert.Unique
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type Phase = AST -> AST
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phases :: Target -> [Phase]
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phases YOSYS =
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[ Convert.AsgnOp.convert
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, Convert.Enum.convert
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, Convert.PackedArray.convert
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, Convert.StarPort.convert
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, Convert.Struct.convert
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, Convert.Return.convert
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, Convert.Typedef.convert
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, Convert.Unique.convert
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]
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phases VTR =
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(phases YOSYS) ++
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[ Convert.AlwaysKW.convert
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, Convert.CaseKW.convert
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, Convert.Logic.convert
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, Convert.SplitPortDecl.convert
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]
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run :: Target -> Phase
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run target = foldr (.) id $ phases target
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convert :: Target -> Phase
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convert target = convert'
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where
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convert' :: Phase
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convert' descriptions =
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if descriptions == descriptions'
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then descriptions
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else convert' descriptions'
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where descriptions' = run target descriptions
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