mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-03 16:39:06 +02:00
12 lines
263 B
Verilog
12 lines
263 B
Verilog
module top;
|
|
initial begin : foo
|
|
reg [1:0] a;
|
|
for (a = 0; a < 3; a++) begin
|
|
if (a == 2'b01 || a == 2'b00)
|
|
$display("fizz");
|
|
if (a == 2'b10)
|
|
$display("buzz");
|
|
end
|
|
end
|
|
endmodule
|