mirror of https://github.com/zachjs/sv2v.git
31 lines
852 B
Systemverilog
31 lines
852 B
Systemverilog
`default_nettype none
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module ALU(
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input logic [2:0] operation,
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input logic [31:0] left, right,
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output logic [31:0] result
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);
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always_comb begin
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result = 32'b0;
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case(operation)
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3'd0: begin
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// Right logical shift
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// Only need the lowest 5 bits for 32 bit input
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result = $unsigned(left) >> right[4:0];
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end
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3'd1: begin
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// Right arithmetic shift
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result = $signed(left) >>> right[4:0];
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end
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3'd2: begin
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// Signed Comparison
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result = $signed(left) < $signed(right);
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end
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3'd3: begin
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// Unsigned comparison
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result = $unsigned(left) < $unsigned(right);
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end
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endcase
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end
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endmodule |