mirror of https://github.com/zachjs/sv2v.git
17 lines
433 B
Systemverilog
17 lines
433 B
Systemverilog
module foo(clock, data);
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input logic clock;
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output logic [10:0] data [5];
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initial data[0][0] = 0;
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always @(clock) begin
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integer i, j;
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for (i = 4; i >= 0; i--) begin
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for (j = 9; j >= 0; j--) begin
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data[i][j + 1] = data[i][j];
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end
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if (i != 0)
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data[i][0] = data[i-1][10];
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end
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data[0][0] = ~data[0][0];
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end
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endmodule
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