mirror of https://github.com/zachjs/sv2v.git
27 lines
493 B
Systemverilog
27 lines
493 B
Systemverilog
module top_a;
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initial $display("top_a");
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mod m();
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endmodule
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module top_b;
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initial $display("top_b");
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intf i();
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sub s(i);
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endmodule
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module mod;
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initial $display("mod");
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endmodule
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interface intf;
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initial $display("intf");
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endinterface
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module sub(interface i);
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initial $display("sub");
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endmodule
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module top_c;
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parameter type T;
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parameter U;
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initial if ($bits(T) == 1) $display("top_c");
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endmodule
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module top_d;
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initial $display("top_d");
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endmodule
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