mirror of https://github.com/zachjs/sv2v.git
41 lines
673 B
Verilog
41 lines
673 B
Verilog
module top;
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initial begin
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$write("Elaboration Info: ");
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$display;
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end
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initial begin
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$write("Elaboration Info: ");
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$display("%b", 1);
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end
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initial begin
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$write("Elaboration Warning: ");
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$display;
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end
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initial begin
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$write("Elaboration Warning: ");
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$display("%b", 2);
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end
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initial begin
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$write("Elaboration Error: ");
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$display;
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end
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initial begin
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$write("Elaboration Error: ");
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$display("%b", 3);
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end
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initial begin
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$display("Elaboration Fatal:");
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$finish;
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end
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initial begin
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$write("Elaboration Fatal: ");
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$display;
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$finish(0);
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end
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initial begin
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$write("Elaboration Fatal: ");
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$display("%b", 4);
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$finish(0);
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end
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endmodule
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