mirror of https://github.com/zachjs/sv2v.git
46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
module example;
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parameter P = 0;
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// needed because of steveicarus/iverilog#528
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`ifdef __ICARUS__
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`define BEGIN begin : `BLK
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`define END end
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`else
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`define BEGIN
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`define END
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`endif
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`define BLK genblk1
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if (P == 1) `BEGIN integer w = 1; `END
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else if (P == 2) `BEGIN integer x = 2; `END
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else if (P == 3) `BEGIN integer y = 3; `END
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else `BEGIN integer z = 9; `END
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`undef BLK
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`define BLK genblk2
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case (P)
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1 : `BEGIN integer w = 1; `END
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2 : `BEGIN integer x = 2; `END
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3 : `BEGIN integer y = 3; `END
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default: `BEGIN integer z = 9; `END
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endcase
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`undef BLK
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`define BLK genblk3
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if (1) `BEGIN wire a = 1; `END
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endmodule
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module top;
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`define TEST(i, v) \
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example #(i) e``i(); \
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initial #i begin \
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$display(`"e``i.genblk1.v: %0d`", e``i.genblk1.v); \
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$display(`"e``i.genblk2.v: %0d`", e``i.genblk2.v); \
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$display(`"e``i.genblk3.a: %0d`", e``i.genblk3.a); \
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end
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`TEST(1, w)
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`TEST(2, x)
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`TEST(3, y)
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`TEST(4, z)
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endmodule
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